The present invention relates in general to a method and apparatus for performing integrated circuit timing which accounts for noise, due to signal coupling. More particularly, in the field of integrated circuit design, the present invention is directed to a method and apparatus which identifies critical nets which could be affected by signal to signal noise, extracts a full circuit topology, including neighboring signals, for those critical nets, determines actual delays, which includes noise from other signals and corrects inputs to a full chip timing run, which more accurately determines the actual operation of the integrated circuit.